In U.S. Pat. No. 4,203,158, Frohman-Bentchkowsky et al. disclose an electrically programmable erasable MOS memory device fabricated on a P-type silicon substrate and including N-type source and drain regions defining a channel therebetween. An electrically floating polysilicon gate is formed above the channel. The floating gate for most of the channel is separated from the substrate by an oxide layer of between 500 .ANG. and 1000 .ANG. thick. A much smaller area of the floating gate is separated from the substrate by a thin oxide layer of between 70 .ANG. and 200 .ANG. thick. This thin oxide layer extends over a third N-type region which is contiguous with the source region. The floating gate also extends over a portion of the third region and is separated from the third region by the thin oxide region. A polysilicon program gate is disposed above the floating gate and insulated therefrom by another oxide layer. The drain region of the memory device may also be a source for a selection transistor whose gate is coupled to a word select line.
The memory device is fabricated by a process in which the overlap of the floating gate with the third region is formed by first growing the thicker gate oxide and then forming a slot in the oxide above the overlap area. The slot is used to diffuse or implant an N-type dopant, such as arsenic, into the third region and also to define the thin oxide layer. Then the floating gate is formed. Alternatively, a separate doping step to define the third region may be avoided by causing sufficient lateral diffusion from the source region to provide the necessary overlap with the floating gate.
In U.S. Pat. No. 4,598,460, Owens et al. disclose a method of making an integrated circuit EPROM having EPROM devices together with N-channel and P-channel peripheral devices, in which independently adjustable thresholds are provided for each of the three device types. The EPROM devices are formed with steps which may include etching through a polysilicon layer, an interpoly oxide layer and another polysilicon layer to form both a control gate and a floating gate beneath it, then implanting N-type arsenic ions adjacent to these gates, using the gates as a self-aligning mask, to form source and drain regions. This may be followed by a phosphorus ion implant into the same source and drain regions using the same mask as was used for the arsenic implant. Since phosphorus has a greater diffusion rate than arsenic, subsequent heating results in the phosphorus outrunning the arsenic and spreading the sources and drains downward and laterally to create a high density core of arsenic ions for good ohmic contact surrounded by a low density shell of phosphorus ions that extend under the floating gate. Drain extension under the floating gate improves programming efficiency. The low density shell also reduces the chances of shorting due to any slight misregistration between metal contacts and the source and drain cores.
An object of the present invention is to provide a fabrication process and memory cell layout for electrically programmable and rapidly erasable MOS memory devices that result in a smaller memory cell size.